35.160 微处理机系统 标准查询与下载
共找到 359 条与 微处理机系统 相关的标准，共 24 页
This International Standard applies to physical connectors and cables, electrical properties, and logical protocols for point-to-point serial scalable interconnect, operating at speeds of 10 Mbit/s to 200 Mbit/s and at 1 Gbit/s in copper and optic technologies (as developed in Open Microprocessor Systems Initiative/Heterogeneous Interconnect Project (OMI/HIC)). The object of this International Standard is to enable high-performance, scalable, modular, parallel systems to be constructed with low system integration cost; to support communications systems fabric; to provide a transparent implementation of a range of high-level protocols (communications, e.g. ATM, message passing, shared memory transactions, etc.), and to support links between heterogeneous systems.
Information Technology - Microprocessor Systems - Heterogeneous InterConnect (HIC) (Low-Cost, Low-Latency Scalable Serial Interconnect for Parallel System Construction)
- ICS
- 35.160
- CCS
- L62
- 发布
- 2000-07
- 实施
This is Amendment 1 to ISO/IEC 11458-1993 (Information technology Microprocessor systems - VICbus Inter-crate cable bus)
Information technology - Microprocessor systems - VICbus; Inter-crate cable bus; Amendment 1
- ICS
- 35.160
- CCS
- L60
- 发布
- 2000-07
- 实施
SBus - Chip and module interconnect bus
SBus - Chip and module interconnect bus
- ICS
- 35.160
- CCS
- L62
- 发布
- 2000-06
- 实施
SBus is a high performance computer I/O interface for connecting integrated circuits and SBus Cards to a computer system motherboard. This standard defines the mechanical, electrical, environmental, and protocol requirements for the design of SBus Cards and the computer system motherboard that supports those cards. Every SBus Card shall implement appropriate self-descriptive and initialization firmware using FCode, which is similar to the Forth programming language. The details of this firmware standard are beyond the scope of this standard. In addition, other software interfaces may be used for communication with SBus Cards. SBus is intended to provide a high performance I/O bus interface with a small mechanical form factor. The small size, high levels of integration, and low power usage of SBus Cards enable them to be used in laptop computers, compact desktop computers, and other applications requiring similar characteristics. SBus Cards are mounted in a plane parallel to the motherboard of the computer system, allowing the computer system to have a low profile. SBus is not designed as a general purpose backplane bus. SBus allows transfers to be in units of 8, 16, 32, or 64 bits. Burst transfers are allowed to further improve performance. SBus allows a number of SBus Master devices to arbitrate for access to the bus. The chosen SBus Master provides a 32-bit virtual address which the SBus Controller maps to the selection of the proper SBus Slave and the development of the 28-bit physical address for that Slave. The selected SBus Slave then performs the data transfers requested by the SBus Master. Simple SBus Cards may be designed to operate solely as Slaves on the SBus. note: 1) A firmware interface standard is under consideration.
SBus - Chip and module interconnect bus
- ICS
- 35.160
- CCS
- L62
- 发布
- 2000-06
- 实施
The document defines a workload in order to make performance values according to DIN 66273-1 universally applicable and comparable between different computer configurations. The workload Type A is designed for a computer centre business which contains a dialogue-oriented system environment and a batch-oriented production flow.
Information processing - Measurement and rating of data processing performance - Part 2: Workload Type A
- ICS
- 35.160
- CCS
- L70
- 发布
- 2000-04
- 实施
Настоящий стандарт устанавливает требования к интерфейсной системе, используемой для взаимного соединения устройств обработки, запомин
IEC 821 VME bus. Microprocessor system bus for 1 byte to 4 byte data
- ICS
- 35.160
- CCS
- 发布
- 2000
- 实施
- 2001-01-01
ISO/IEC 15205:2000 (IEEE Std 1496-1993) SBus - Chip and Module Interconnect Bus
- ICS
- 35.160
- CCS
- 发布
- 2000
- 实施
This International Standard specifies the logical specifications of STbus which is a high-performance and highly reliable system bus. STbus adopts a synchronous transfer method with a high-speed clock and a split transfer method enabling to minimize bus holding time during one bus operation and to use a bus efficiently. The contents given in this specifications are as follows: a) System bus interface signal provisions; b) Bus operations and transfer protocol for each bus operation; c) Copyback cache coherency control for maintaining consistency between a shared memory and a cache memory of each processor in a multiprocessor system; d) Fault detection function using parity check and duplex configuration for control signals.
Information technology - Synchronous split transfer type system bus (Stbus) - Logical layer
- ICS
- 35.160
- CCS
- M11
- 发布
- 1999-12
- 实施
CEBus-EIB Router Medium Access Control Sublayer
- ICS
- 35.160
- CCS
- L60
- 发布
- 1999
- 实施
The basic dimensions of a range of modular subracks conforming to 60297-3 (1984-01) and 60297-4 (1995-03) for mounting in equipment according to 60297-1 (1986-09) and 310-D-1992, together with the basic dimensions of a compatible range of plug-in units, printed boards, and backplanes, are covered. The dimensions and tolerances necessary to ensure mechanical function compatibility are provided. This standard offers total system integration guidelines with attendant advantages, such as reduction in design and development time, manufacturing cost savings, and distinct marketing advantages.
Standard for Mechanical Core Specifications for Microcomputers Using IEC 60603-2 Connectors IEEE Computer Society Document
- ICS
- 35.160
- CCS
- L63
- 发布
- 1998-09-28
- 实施
この規格は，高性能，高信頼なシステムバスであるSTbusの論理仕様を規定している。STbusは高速クロックに同期した転送方式と，バスの無効保留時間を削減しバスを効率ょく使用できるスプリット転送方式を採用している。この規格では，主に以下の内容を規定している。
Synchronous split transfer type system bus (STbus) -- Logical layer
- ICS
- 35.160
- CCS
- L62
- 发布
- 1998-03-20
- 实施
本规范规定了舰船电子设备机箱、机拒的设计、制造、检验、包装、运输、贮存和安装的通用要求。 本规范适用于舰船上的雷达、声纳、指控、电子对抗、导航、通信等电子设备的机箱、机柜。
General specification for cases and enclosures of shipborne electronic equipment
- ICS
- 35.160
- CCS
- L62
- 发布
- 1998-03-20
- 实施
- 1998-08-01
Defines a protocol for the transport of commands and data over high performance serial bus, as specified in American National Standard for High Performance Serial Bus, ANSI/IEEE1394-1995. The transport protocol, Serial Bus Protocol 2 or SBP-2, requires implementations to conform to the requirements of the aforementioned standard as well as to International Standard for Control and Status Register (CSR) Architecture for Microcomputer Buses, ISO/IEC 13213:1994, and permits the exchange of commands, data and status between initiators and targets connected to Serial Bus.
Information Technology - Serial Bus Protocol 2 (SBP-2)
- ICS
- 35.160
- CCS
- L74
- 发布
- 1998-01-01
- 实施
Specifies dimensions that will ensure mechanical interchangeability of rear-mounted plug-In units (Transition Modules) in sub-racks based on American National Standard for Mechanical Core Specifications for Microcomputers Using IEC 603-2 Connectors, ANSI/IEEE 1101.1-1992; American National Standard for Additional Mechanical Specifications for Microcomputers Using the IEEE 1101.1 Equipment Practice, ANSI 1101.10-1996; IEC 297-3; and IEC 297-4.
Standard for Mechanical Rear Plug-in Units Specifications for Microcomputers Using IEEE 1101.1 and IEEE 1101.10 Equipment Practice
- ICS
- 35.160
- CCS
- L62
- 发布
- 1998
- 实施
INFORMATION TECHNOLOGY - MICROPROCESSOR SYSTEMS - VICbus - INTER-CRATE CABLE BUS
- ICS
- 35.160
- CCS
- 发布
- 1997-12-09
- 实施
INFORMATION TECHNOLOGY - MICROPROCESSOR SYSTEMS - FUTUREBUS＋ - LOGICAL PROTOCOL SPECIFICATION
- ICS
- 35.160
- CCS
- 发布
- 1997-12-09
- 实施
This standard specifices a high performance backplane bus for use in microcomputer systems that employ single or multiple microprocessors. It is based on the VMEbus specification, released by the VME Manufacturers Group in August of 1982. The bus includes four sub-buses: the Data Transfer Bus, the Priority Interrupt Bus, the Arbitration Bus and the Utility Bus.
IEC 821 VMEbus - Microprocessor system bus for 1 byte to 4 byte data
- ICS
- 35.160
- CCS
- 发布
- 1997-07-08
- 实施
- 1997-03-12
The overall level of performance that may be achieved by any computer system is determined, in large part, by the system bus that is used to effect communication between the various system elements. System performance characteristics, measured in terms of speed, reliability, suitability to a variety of purposes, and adaptability to changing technology are ultimately dependent on the particular bus structure that is used and its associated protocols. This standard defines the IEEE Std 1000 Bus, which may be used to implement general purpose, high-performance 8-bit microcomputer systems. Such a system may be used in a stand-alone configuration, or in larger multiple-bus architectures, as a private (or secondary) bus or a high-speed I/O channel. This standard is applicable to those systems and system elements with the common commercial designation STEbus. It is intended for those users who plan to evaluate, implement, or design various system elements that are compatible with the IEEE 1000 Std Bus system structure. The physical attributes and method of interconnect utilized by boards and modules conforming to this standard are derived from several International Electrotechnical Commission (IEC) standards. These standards, when implemented jointly in a systems environment, result in a mechanical configuration commonly referred to as Eurocard. Appendix B lists such applicable standards which, where referenced, are considered as if incorporated with this standard. In particular, the connector used by IEEE Std 1000 Bus boards is a 64-pin male connector utilizing the outside two rows (designated a and c rows), specified in IEC 60603-2, and the mating female connector is used on IEEE Std 1000 Bus backplanes. The recommended size for IEEE Std 1000 Bus boards is 100 mm×160 mm (3,937 in×6,299 in), commonly referred to as a single height standard depth Eurocard. The IEEE Std 1000 Bus structure is based on the master-slave concept in which a master, having gained control of the bus, may address and command slaves. Masters and slaves communicate with each other by use of an asynchronous interlocked handshake protocol. This technique allows for the construction of computer systems that incorporate devices of widely varying speeds. Multiple masters may be implemented within a single system. Two independent address spaces are supported: memory and I/O. Memory transactions reference a 1 megabyte physical address space, while I/O transactions reference a 4 kilobyte physical address space. System integrity during all such transactions is enhanced by provision of a transfer error signal. Provision is made for interboard condition alerts such as interrupt requests, DMA requests, system-specific error conditions, or other specialized status conditions. Within this scheme eight prioritized attention request levels, each with vectored response capability, are available for user assignation. This standard deals only with those characteristics that must be specified so as to ensure the successful design and implementation of compatible boards and systems. Issues relating to individual design specifications, and performance or safety requirements are not addressed.
Information technology - 8-bit backplane interface: STEbus and mechanical core specifications for microcomputers
- ICS
- 35.160
- CCS
- L60
- 发布
- 1997-06
- 实施
