IEEE 1800-2017
SystemVerilog-统一硬件设计 规范 和验证语言（IEEE计算机协会）

SystemVerilog-Unified Hardware Design@ Specification@ and Verification Language (IEEE Computer Society)

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标准号

IEEE 1800-2017

发布

2017年

发布单位

IEEE - The Institute of Electrical and Electronics Engineers@ Inc.

当前最新

IEEE 1800-2017

 

 

适用范围

This standard provides the definition of the language syntax and semantics for the IEEE 1800? SystemVerilog language@ which is a unified hardware design@ specification@ and verification language. The standard includes support for behavioral@ register transfer level (RTL)@ and gate-level hardware descriptions; testbench@ coverage@ assertion@ object-oriented@ and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages. Purpose This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification@ design@ and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design@ improve verification@ and enhance cross-language interactions.

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