The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this...
IEEE Std 1800.2-2020由美国电气电子工程师学会 US-IEEE 发布于 2020-09-14,并于 2020-09-14 实施。
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