IEEE Unapproved Draft Std P1800/D8, Feb, 2009

IEEE Draft Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language

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标准号

IEEE Unapproved Draft Std P1800/D8, Feb, 2009

发布

2009年

发布单位

美国电气电子工程师学会

 

 

适用范围

This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog ...

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