This standard represents a merger of two previous standards: IEEE Std 1364-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unifiedhardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be usedas one language. Merging the base Verilog langua...
IEEE P1800/D5, February 2012由美国电气电子工程师学会 US-IEEE 发布于 2012-02-22,并于 2012-02-22 实施。
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