Defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.