Recommendations are provided for the layout and test methods required to characterize properly latchup behavior in CMOS and BiCMOS integrated circuit processes or other processes that have similar lateral PNPN topographical layout characteristics. The aim is to allow the characterization of an integrated circuit process architecture so that different approaches can be scientifically compared. This...
IEEE Std 1181-1991由美国电气电子工程师学会 US-IEEE 发布于 1991-04-19,并于 1991-04-19 实施。
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