IEC 62751-2:2014+AMD1:2019+AMD2:2023 CSV 标准

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适用范围: IEC 62751-2:2014+AMD1:2019+AMD2:2023 gives the detailed method to be adopted for calculating the power losses in the valves for an HVDC system based on the "modular multi-level converter", where each valve in the converter consists of a number of self-contained, two-terminal controllable voltage sources connected in series. It is applicable both for the cases where each modular cell uses only a single turn-off semiconductor device in each switch position, and the case where each switch position consists of a number of turn-off semiconductor devices in series (topology also referred to as "cascaded two-level converter"). The main formulae are given for the two-level "half-bridge" configuration but guidance is also given as to how to extend the results to certain other types of MMC building block configuration.

IEC 62751-2:2014+AMD1:2019+AMD2:2023 CSV