1076.3-1997

Standard VHDL Synthesis Packages (IEEE Computer Society Document; Includes Access to Additional Content)


 

 

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标准号
1076.3-1997
发布日期
1997年03月20日
实施日期
2015年03月14日
废止日期
中国标准分类号
/
国际标准分类号
/
发布单位
IEEE - The Institute of Electrical and Electronics Engineers@ Inc.
引用标准
49
适用范围
This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:a) The hardware interpretation of values belonging to the BIT and BOOLEAN types defined by IEEE Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.b) A function (STD_MATCH) that provides "donapos;t care" or "wild card" testing of values based on the STD_ULOGIC type. c) Standard functions for representing sensitivity to the edge of a signal.d) Two packages that define vector types for representing signed and unsigned arithmetic values@ and that define arithmetic@ shift@ and type conversion operations on those types.This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition@ IEEE Std 1076-1987@ are described in 7.2.




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