Purpose and scope This standard defines IEC 61691-6/IEEE 1076.1? language@ a hardware description language for the description and the simulation of analog@ digital@ and mixed-signal systems. The language@ also informally known as VHDLAMS@ is built on the IEC 61691-1-1/IEEE 1076? (VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models. This document contains the complete reference of the IEC 61691-6/IEEE 1076.1 VHDL language@ including the unchanged portions of the base language and the extensions. Formally@ IEC 61691-6:2009/IEEE Std 1076.1-2007 defines the extensions only@ and portions of text marked with change bars are either exclusively part of IEC 61691-6:2009/IEEE Std 1076.1-2007 or define changes compared to IEC 61691-1-1:2004/IEEE Std 1076-2002.1 Portions of text not marked with change bars are identical in this document and in IEC 61691-1-1:2004/IEEE Std 1076-2002. The primary audience of this document are implementers of tools supporting the language and advanced users of the language. The document is not intended to provide any introductory or tutorial information. It rather provides formal definitions of language elements and language constructs. The IEC 61691-6/IEEE 1076.1 language is a superset of the IEC 61691-1-1/IEEE 1076 language (VHDL). As such@ any legal IEC 61691-1-1/IEEE 1076 model is a IEC 61691-6/IEEE 1076.1 model@ and any IEC 61691-6/IEEE 1076.1 tool shall provide the same simulation results as obtained with an IEC 61691-1-1/IEEE 1076 tool. IEC 61691-1-1:2004/IEEE Std 1076-2002 and IEC 61691-6:2009/IEEE Std 1076.1-2007 will remain separate standards. This means that when IEC 61691-1-1:2004/IEEE Std 1076-2002 is revised@ IEC 61691-6:2009/IEEE Std 1076.1-2007 will not be automatically revised accordingly. A separate effort will be required to keep both standards synchronized and to avoid inconsistencies. 1 Information on references can be found in 0.2.