1800.2-2017 发布历史

This standard establishes the Universal Verification Methodology (UVM)@ a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular@ scalable@ and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog@ IEEE Std 1800?.1 Purpose Verification components and environments are currently created in different forms@ making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool@ as well as make it easier to reuse verification components. Overall@ the UVM standardization effort will lower verification costs and improve design quality throughout the industry

1800.2-2017由IEEE - The Institute of Electrical and Electronics Engineers@ Inc. 发布于 2017-02-14，并于 2017-05-20 实施。

1800.2-2017 发布之时，引用了标准

1800.2-2017的历代版本如下：

2017年02月14日 1800.2-2017

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标准号: 1800.2-2017
发布日期: 2017年02月14日
实施日期: 2017年05月20日
废止日期: 无
中国标准分类号: /
国际标准分类号: /
发布单位: IEEE - The Institute of Electrical and Electronics Engineers@ Inc.
引用标准: 472

适用范围: This standard establishes the Universal Verification Methodology (UVM)@ a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular@ scalable@ and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog@ IEEE Std 1800?.1 Purpose Verification components and environments are currently created in different forms@ making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool@ as well as make it easier to reuse verification components. Overall@ the UVM standardization effort will lower verification costs and improve design quality throughout the industry

1800.2-2017

Universal Verification Methodology Language Reference Manual (IEEE Computer Society)