This standard defines extensions to IEEE Std 1149.1? to standardize the boundary-scan structures and methods required to help ensure simple@ robust@ and minimally intrusive boundary-scan testing of advanced digital networks.1 Such networks are not adequately addressed by existing standards@ especially for those networks that are ac-coupled@ differential@ or both. Testing enabled by this standard will operate in parallel with IEEE Std 1149.1 testing of conventional digital networks and in conjunction with IEEE Std 1149.4? testing of conventional analog networks. This standard also specifies software and Boundary-Scan Description Language (BSDL) extensions to IEEE Std 1149.1@ which are required to support new I/O test structures. Purpose Existing boundary-scan test standards (IEEE Std 1149.1@ IEEE Std 1149.4) do not fully address some of the increasingly common@ newer digital network topologies@ such as ac-coupled@ differential interconnections on very high speed (1+ Gb/s) digital data paths. IEEE Std 1149.1 structures and methods are intended to test static (dc-coupled)@ single-ended networks. They are unable to test dynamic (ac-coupled) digital networks@ since ac coupling blocks static signals. Differential networks are also inadequately tested by IEEE Std 1149.1@ which requires either the insertion of boundary cells between the differential driver or receiver and the chip pads (this often creates an unacceptable performance degradation)@ or insertion of single boundary cells before the differential driver and after the differential receiver (this reduces controllability and observability to the point that many board assembly defects cannot be detected). IEEE Std 1149.4 structures and methods are intended for testing analog networks@ and in most cases are not able to test these newer digital networks as well. Specifically@ IEEE Std 1149.4 provides the opportunity to inject dynamic (time-varying) or analog signals for test@ but these structures intended for analog testing are often too intrusive (too high an impact on performance and pin count) for high speed chip designs@ and require additional resources and test application time not otherwise required for testing digital circuits. Finally@ very high-speed logic imposes new restrictions on test structures that were not considered in IEEE Std 1149.1. 1 Information of references can be found in Clause 2.