IEEE - The Institute of Electrical and Electronics Engineers@ Inc.
引用标准
862
适用范围
Objectives of this standard The intent of this standard is to serve as a complete specification of the Verilog ? Hardware Description Language (HDL). This document contains ?? The formal syntax and semantics of all Verilog HDL constructs ?? The formal syntax and semantics of Standard Delay Format (SDF) constructs ?? Simulation system tasks and functions@ such as text output display commands ?? Compiler directives@ such as text substitution macros and simulation time scaling ?? The Programming Language Interface (PLI) binding mechanism ?? The formal syntax and semantics of access routines@ task/function routines@ and Verilog procedural interface routines ?? Informative usage examples ?? Informative delay model for SDF ?? Listings of header files for PLI