The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained...
IEEE Std 1800-2012由美国电气电子工程师学会 US-IEEE 发布于 2013-02-21,并于 2013-02-21 实施。
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