IEC 62530:2007 (E)
IEC 62530 版 1 (IEEE Std 1800(TM)-2005)：SystemVerilog 标准 统一硬件设计、规范和验证语言

IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language

IEC 62530:2007 (E) 发布历史

IEC 62530:2007 (E)由美国电气电子工程师学会 US-IEEE 发布于 2007-12-09，并于 2007-12-09 实施。

This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware description language (HDL) to aid in the creation and verification of abstract architectural level models. It also includes design specification methods, embedded assertions language, testbench language including coverage and an assertions application programming interface (API), and a direct programming interface (DPI)...

标准号

IEC 62530:2007 (E)

发布

2007年

发布单位

美国电气电子工程师学会

 

 

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