31.080.20 晶体闸流管 标准查询与下载

TIS 1975-2000 半导体器件.分立器件.第6部分:晶闸管.第3节:电流在100A以上的环境和外壳额定的反向阻断三极闸流晶体管空白详细规范

Semiconductor devices discrete devices.part 6: thyristors section 3: blank detail specification for reverse blocking triode thyristors, ambient and case.rated, for currents greater than 100 a

BS EN 61954:2011+A1:2013 静止无功补偿器(SVC).晶闸管阀测试

Static VAR compensators (SVC). Testing of thyristor valves

DIN EN 61975:2011 高压直流系统装置.系统试验(IEC 61975-2010);德文版本EN 61975-2010

High-voltage direct current (HVDC) installations - System tests (IEC 61975:2010); German version EN 61975:2010

TIS 1972-2009 半导体器件.第6部分:晶闸管

Semiconductor devieces.part 6: thyristors

DIN EN 60700-1:2009 压直流(HVDC)电力传输用可控硅阀.第1部分:电气试验(IEC 60700-1:1998 + A1:2003 + A2:2008),德文版本EN 60700-1:1998 + A1:2003 + A2:2008

Thyristor valves for high voltage direct current (HVDC) power transmission - Part 1: Electrical testing (IEC 60700-1:1998 + A1:2003 + A2:2008); German version EN 60700-1:1998 + A1:2003 + A2:2008

NF C53-700-1/A2:2009 高压直流(HVDC)电力传输用晶体闸流管阀门.第1部分:电气测试

Thyristor valves for high-voltage direct current (HVDC) power transmission - Part 1 : electrical testing.

IEC 60700-1:1998+AMD1:2003+AMD2:2008 CSV 高压直流输电用晶闸管阀第1部分:电气试验

Thyristor valves for high voltage direct current (HVDC) power transmission - Part 1: Electrical testing

IEC 60700-1:1998/AMD2:2008 高压直流电(HVDC)电力传输用半导体闸流管阀.第1部分:电气测试

This amendment has been prepared by subcommittee 22F: Power electronics for electrical transmission and distribution systems, of IEC technical committee 22: Power electronic systems and equipment. The text of this amendment is based on the following documents: Full information on the voting for the approval of this amendment can be found in the report on voting indicated in the above table. The committee has decided that the contents of this amendment and the base publication will remain unchanged until the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in the data related to the specific publication. At this date, the publication will be reconfirmed. ~ reconfirmed, ~ withdrawn, ~ replaced by a revised edition, or ~ amended.

Thyristor valves for high-voltage direct current (HVDC) power transmission - Part 1: Electrical testing

JEDEC JESD82-27-2007 SSTUB32869的定义 DDR2 RDIMM注册的应用缓冲器的单双校验

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications.

Definition of the SSTUB32869 Registered Applications Buffer with Parity for DDR2 RDIMM

JEDEC JESD82-24-2007 SSTUB32865的定义 DDR2 RDIMM应用软件28位1:2注册缓冲器加奇偶校验

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32865 registered buffer with parity for 2 rank by 4 or similar highdensity DDR2 RDIMM applications. The SSTUB32865 is identical in functionality to the SSTU32865 but specifies tighter timing characteristics and a higher application frequency of up to 410MHz.

Definition of the SSTUB32865 for DDR2 RDIMM Applications 28-bit 1:2 Registered Buffer with Parity

JEDEC JESD82-26-2007 SSTUB32868的定义 2Rx4DDR2 RDIMM应用软件的注册缓冲器的单双校验

Definition of the SSTUB32868 Registered Buffer with Parity for 2R x 4 DDR2 RDIMM Applications

Definition of the SSTUB32868 Registered Buffer with Parity for 2R x 4 DDR2 RDIMM Applications

JEDEC JESD82-25-2007 SSTUB32866的定义 4DDR2 RDIMM应用软件1.8V可配置的注册缓冲器加奇偶校验测试

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32866 registered buffer with parity test for DDR2 RDIMM applications.

Definition of the SSTUB32866 1.8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications

JEDEC JESD82-19A-2007 SSTUA32S865的定义 DDR2 RDIMM应用软件 注册的缓冲器加奇偶校验和SSTUA32D865 28位1:2

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32S865 and SSTUA32D865 registered buffer with parity for 2 rank by 4 or similar high-density DDR2 RDIMM applications.

Definition of the SSTUA32S865 DDR2 RDIMM Applications Registered Buffer with Parity for and SSTUA32D865 28-bit 1:2

JEDEC JESD82-16A-2007 SSTUB32866的定义 DDR2 RDIMM应用软件28位1:2注册缓冲器加奇偶校验测试

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity is designed for 1.7 V to 1.9 V VDD operation.

Definition of the SSTUA32866 1.8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications

JEDEC JESD82-9B-2007 SSTU32865的定义 2R x 4 DDR2 RDIMM应用软件的注册缓冲器加奇偶校验

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32865 registered buffer with parity for 2 rank by 4 or similar highdensity DDR2 RDIMM applications.

Definition of the SSTU32865 Registered Buffer with Parity for 2R ?4 DDR2 RDIMM Applications

JEDEC JESD82-10A-2007 SSTU32866的定义 DDR2 RDIMM应用软件28位1:2注册缓冲器加奇偶校验测试

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32866 registered buffer with parity test for DDR2 RDIMM applications.

Definition of the SSTU32866 1.8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications

JEDEC JESD82-23-2007 SSTUB32S869和SSTUA32D869的定义 DDR2 RDIMM应用软件注册缓冲器加奇偶校验

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUA32S869 and SSTUA32D869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. The SSTUA32S869 and SSTUA32D869 are identical in functionality to the SSTU32S869 and SSTU32D869 devices respectively but specify tighter timing characteristics and a higher application frequency of up to 410MHz.

Definition of the SSTUA32S869 and SSTUA32D869 DDR2 RDIMM Applications Registered Buffer with Parity for

JEDEC JESD82-12A-2007 SSTU32S869和SSTU32D869的定义 DDR2 RDIMM应用软件的注册缓冲器加奇偶校验

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTU32S869 and SSTU32D869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM.

Definition of the SSTU32S869 and SSTU32D869 Registered Buffer with Parity for DDR2 RDIMM Applications

JEDEC JESD82-20-2007 FBDIMM: 高级存储缓冲器(AMB)

This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided.

FBDIMM: Advanced Memory Buffer (AMB)

JEDEC JESD74A-2007 半导体器件的早期寿命故障运价计算程序

Early life failure rate (ELFR) measurement of a product is typically performed during product qualifications or as part of ongoing product reliability monitoring activities. These tests measure reliability performance over the product’s first several months in the field. It is therefore important to establish a methodology that will accurately project early life failure rate to actual customer use conditions.

Early Life Failure Rate Calculation Procedure for Semiconductor Components