IEEE P1800/D18, August 2023由美国电气电子工程师学会 US-IEEE 发布于 2023-09-08,并于 2023-09-08 实施。
The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing test benches using coverage, assertions, object-oriented programming, and constraine...
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