L40 半导体分立器件综合 标准查询与下载

IEC 62258-2:2011 半导体压模产品.第2部分:交换数据格式

Semiconductor die products - Part 2: Exchange data formats

IEC 60749-30:2005/AMD1:2011 半导体器件.机械和气候试验方法.第30部分:先于可靠性测试的非密封性表面贴装设备的预处理

Semiconductor devices - Mechanical and climatic test methods - Part 30: Preconditioning of non-hermetic surface mount devices prior to reliability testing

DIN EN 60749-34:2011 半导体器件.机械和气候试验方法.第34部分:电力循环(IEC 60749-34-2010).德文版本EN 60749-34-2010

Semiconductor devices - Mechanical and climatic test methods - Part 34: Power cycling (IEC 60749-34:2010); German version EN 60749-34:2010

NF C96-022-15*NF EN 60749-15:2011 半导体器件.机械和环境测试方法.第15部分:引脚插入式封装设备的耐钎焊温度.

Semiconductor devices - Mechanical and climatic test methods - Part 15 : resistance to soldering temperature for through-hole mounted devices.

IEC 60749-29:2011 半导体器件.机械和气候试验方法.第29部分:闭锁试验

"Scope and object This part of IEC 60749 covers the I-test and the overvoltage latch-up testing of integrated circuits. This test is classified as destructive. The purpose of this test is to establish a method for determining integrated circuit (IC) latchup characteristics and to define latch-up failure criteria. Latch-up characteristics are used in determining product reliability and minimizing ""no trouble found"" (NTF) and ""electrical overstress"" (EOS) failures due to latch-up. This test method is primarily applicable to CMOS devices. Applicability to other technologies must be established. The classification of latch-up as a function of temperature is defined in 3.1 and the failure level criteria are defined in 3.2"

Semiconductor devices - Mechanical and climatic test methods - Part 29: Latch-up test

DIN EN 62258-1:2011 半导体压模产品.第1部分:采购和使用(IEC 62258-1-2009).德文版本EN 62258-1-2010

Semiconductor die products - Part 1: Procurement and use (IEC 62258-1:2009); German version EN 62258-1:2010

IEC 60749-21:2011 半导体器件.机械和气候试验方法.第21部分:可焊性

Semiconductor devices - Mechanical and climatic test methods - Part 21: Solderability

DIN EN 60191-6-21:2011 半导体器件的机械标准化.第6-21部分:表面安装半导体器件封装外形图绘制的一般规则.小外形封装(SOJ)的封装尺寸规格测量方法(IEC 60191-6

Mechanical standardization of semiconductor devices - Part 6-21: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline packages (SOP) (IEC 60191-6

IEC 60749-23:2011 半导体器件.机械和气候试验方法.第23部分:高温下的工作寿命

Semiconductor devices - Mechanical and climatic test methods - Part 23: High temperature operating life

IEC 62047-8:2011 半导体装置.微电机装置.第8部分:薄膜的拉力特性测量的带状抗弯试验方法

This international standard specifies the strip bending test method to measure tensile properties of thin films with high accuracy@ repeatability@ moderate effort of alignment and handling compared to the conventional tensile test. This testing method is valid for test pieces with a thickness between 50 nm and several mm@ and with an aspect ratio (ratio of length to thickness) of more than 300. The hanging strip (or bridge) between two fixed supports are widely adopted in MEMS or micro-machines. It is much easier to fabricate these strips than the conventional tensile test pieces. The test procedures are so simple to be readily automated. This international standard can be utilized as a quality control test for MEMS production since its testing throughput is very high compared to the conventional tensile test.

Semiconductor devices - Micro-electromechanical devices - Part 8: Strip bending test method for tensile property measurement of thin films

DIN EN 62047-4:2011 半导体器件.微电机器件.第4部分:MEMS一般要求(IEC 62047-4-2008);德文版本EN 62047-4-2010

Semiconductor devices - Micro-electromechanical devices - Part 4: Generic specification for MEMS (IEC 62047-4:2008); German version EN 62047-4:2010

DIN EN 60191-6-20:2011 半导体器件的机械标准化.第6-20部分:表面安装半导体器件封装外形图绘制的一般规则.小外形J-引线封装(SOJ)的封装尺寸规格测量方法(IEC

Mechanical standardization of semiconductor devices - Part 6-20: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ) (IEC

BS IEC 60747-14-4:2011 半导体器件.分立器件.半导体加速器

Semiconductor devices. Discrete devices. Semiconductor accelerometers

BS EN 60749-34:2010 半导体器件.机械和环境测试方法.动力循环

Semiconductor devices. Mechanical and climatic test methods. Power cycling

BS EN 60749-15:2010 半导体器件.机械和气候试验方法.穿孔安装设备的耐焊接温度性

This part of IEC 60749 describes a test used to determine whether encapsulated solid state devices used for through-hole mounting can withstand the effects of the temperature to which they are subjected during soldering of their leads by using wave soldering or a soldering iron. In order to establish a standard test procedure for the most reproducible methods, the solder dip method is used because of its more controllable conditions. This procedure determines whether devices are capable of withstanding the soldering temperature encountered in printed wiring board assembly operations, without degrading their electrical characteristics or internal connections. This test is destructive and may be used for qualification, lot acceptance and as a product monitor. This test is, in general, in conformity with IEC 60068-2-20 but, due to specific requirements of semiconductors, the clauses of this standard apply.

Semiconductor devices. Mechanical and climatic test methods. Resistance to soldering temperature for through-hole mounted devices

DIN EN 60749-19:2011 半导体器件.机械和气候试验方法.第19部分:晶片抗切强度(IEC 60749-19-2003 + A1-2010);德文版本EN 60749-19-2003 + A1-2010

Semiconductor devices - Mechanical and climatic test methods - Part 19: Die shear strength (IEC 60749-19:2003 + A1:2010); German version EN 60749-19:2003 + A1:2010

DIN EN 60749-32:2011 半导体器件.机械和气候试验方法.第32部分:塑料封装器件的易燃性(内部引起的)(IEC 60749-32-2002 + Cor.-2003 + A1-2010);德文版本EN 60749-32-2003 + Cor.-2003 + A1-2010

Semiconductor devices - Mechanical and climatic test methods - Part 32: Flammability of plastic-encapsulated devices (externally induced) (IEC 60749-32:2002 + Cor. :2003 + A1:2010); German version EN 60749-32:2003 + Cor. :2003 + A1:2010

IEC 60191-6-17:2011 半导体器件的机械标准化 第6-17部分 表面安装半导体器件封装外形图绘制的一般规则 堆叠式封装的设计指南 精细倾斜球状网阵排列和精细栅格阵列(P-PFBGA和P-PFLAGA)

This part of IEC 60191 provides outline drawings and dimensions for stacked packages and individual stackable packages in the form of FBGA or FLGA.

Mechanical standardization of semiconductor devices - Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land gr

ASTM F1893-11 测量半导体器件电离剂量率存活性和烧断的指南

The use of FXR or LINAC radiation sources for the determination of high dose-rate burnout in semiconductor devices is addressed in this guide. The goal of this guide is to provide a systematic approach to testing semiconductor devices for burnout or survivability. The different types of failure modes that are possible are defined and discussed in this guide. Specifically, failure can be defined by a change in device parameters, or by a catastrophic failure of the device. This guide can be used to determine if a device survives (that is, continues to operate and function within the specified performance parameters) when irradiated to a predetermined dose-rate level; or, the guide can be used to determine the dose-rate burnout failure level (that is, the minimum dose rate at which burnout failure occurs). However, since this latter test is destructive, the minimum dose-rate burnout failure level must be determined statistically.1.1 This guide defines the detailed requirements for testing semiconductor devices for short-pulse high dose-rate ionization-induced survivability and burnout failure. The test facility shall be capable of providing the necessary dose rates to perform the measurements. Typically, large flash X-ray (FXR) machines operated in the photon mode, or FXR e-beam facilities are utilized because of their high dose-rate capabilities. Electron Linear Accelerators (LINACs) may be used if the dose rate is sufficient. Two modes of test are described: (1) A survivability test, and (2) A burnout failure level test. 1.2 The values stated in International System of Units (SI) are to be regarded as standard. No other units of measurement are included in this standard.

Guide for Measurement of Ionizing Dose-Rate Survivability and Burnout of Semiconductor Devices

ASTM F1192-11 半导体装置重离子辐照导致的单粒子效应现象(SEP)测量的标准指南

Many modern integrated circuits, power transistors, and other devices experience SEP when exposed to cosmic rays in interplanetary space, in satellite orbits or during a short passage through trapped radiation belts. It is essential to be able to predict the SEP rate for a specific environment in order to establish proper techniques to counter the effects of such upsets in proposed systems. As the technology moves toward higher density ICs, the problem is likely to become even more acute. This guide is intended to assist experimenters in performing ground tests to yield data enabling SEP predictions to be made. 1.1 This guide defines the requirements and procedures for testing integrated circuits and other devices for the effects of single event phenomena (SEP) induced by irradiation with heavy ions having an atomic number Z ≥ 2. This description specifically excludes the effects of neutrons, protons, and other lighter particles that may induce SEP via another mechanism. SEP includes any manifestation of upset induced by a single ion strike, including soft errors (one or more simultaneous reversible bit flips), hard errors (irreversible bit flips), latchup (persistent high conducting state), transients induced in combinatorial devices which may introduce a soft error in nearby circuits, power field effect transistor (FET) burn-out and gate rupture. This test may be considered to be destructive because it often involves the removal of device lids prior to irradiation. Bit flips are usually associated with digital devices and latchup is usually confined to bulk complementary metal oxide semiconductor, (CMOS) devices, but heavy ion induced SEP is also observed in combinatorial logic programmable read only memory, (PROMs), and certain linear devices that may respond to a heavy ion induced charge transient. Power transistors may be tested by the procedure called out in Method 1080 of MIL STD 750. 1.2 The procedures described here can be used to simulate and predict SEP arising from the natural space environment, including galactic cosmic rays, planetary trapped ions, and solar flares. The techniques do not, however, simulate heavy ion beam effects proposed for military programs. The end product of the test is a plot of the SEP cross section (the number of upsets per unit fluence) as a function of ion LET (linear energy transfer or ionization deposited along the ion''s path through the semiconductor). This data can be combined with the system''s heavy ion environment to estimate a system upset rate. 1.3 Although protons can cause SEP, they are not included in this guide. A separate guide addressing proton induced SEP is being considered. 1.4 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard. 1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices